1. Field of the Invention
The present invention relates generally to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) within integrated circuits. More particularly, the present invention relates to methods for forming MOSFETs within integrated circuits, which MOSFETs exhibit improved hot carrier immunity.
2. Description of the Related Art
Correlating with the increases in density of advanced integrated circuit devices within advanced integrated circuits, and the decreases in dimensions of those advanced integrated circuit devices, there has been a simultaneous evolution of novel effects which affect the performance of advanced integrated circuit devices within advanced integrated circuits. For example, within advanced integrated circuits within which are formed MOSFETs, a general category of novel effects is known as Short Channel Effects (SCEs). Short Channel Effects (SCEs) derive from several factors, including but not limited to: (1) the narrowing of the semiconductor channel beneath a gate oxide within an advanced MOSFET, and (2) the thinning of the gate oxide layer which resides beneath a gate electrode within a MOSFET.
One of the more prevalent Short Channel Effects (SCEs) is the Hot Carrier Effect (HCE). The Hot Carrier Effect (HCE) derives from increased electric fields at gate electrode edges in advanced MOSFETs. The Hot Carrier Effect (HCE) is typically encountered when the thickness of the gate oxide layer within a MOSFET has been reduced while the MOSFET operating voltage has remained constant. As a result of the increased electrical field, charge carriers are injected from the semiconductor substrate within and upon which is formed the MOSFET into the gate oxide layer of the MOSFET, where the charge carriers are captured by free electron states of the gate oxide material from which is formed the gate oxide layer. The Hot Carrier Effect (HCE) is typically manifested as increased sub-threshold currents within the MOSFETs within which is present the Hot Carrier Effect (HCE).
There are several methods by which Hot Carrier Effects (HCEs) may be controlled in advanced MOSFETs. Included among these methods are: (1) reducing the MOSFET operating voltage, (2) increasing the gate oxide layer thickness within the MOSFET, and (3) incorporating a Lightly Doped Drain (LDD) ion implant structure into the semiconductor substrate upon which is formed the MOSFET. A Lightly Doped Drain (LDD) ion implant structure is formed into a portion of the semiconductor substrate which bridges the source/drain electrodes of the MOSFET to the gate electrode edges of the MOSFET, thus providing an electric field gradient less likely to accelerate charge carriers from the semiconductor substrate into the gate dielectric layer.
Of the methods outlined above, the use of the Lightly Doped Drain (LDD) ion implant structure to reduce the Hot Carrier Effect (HCE) has been most common within advanced MOSFETs. Although the use of Lightly Doped Drain (LDD) ion implant structures has provided MOSFETs with reduced susceptibility to Hot Carrier Effects (HCEs), the Hot Carrier Effect (HCE) is not necessarily completely eliminated within MOSFETs within which are incorporated Lightly Doped Drain (LDD) ion implant structures. Thus, it is desirable in the art to provide adjunct methods and structures which supplement Lightly Doped Drain (LDD) ion implant structures in controlling the Hot Carrier Effect (HCE) in advanced MOSFETs. It is towards that goal that the present invention is directed.
Although not necessarily related to the Hot Carrier Effect (HCE), various aspects of forming MOSFETs within integrated circuits are known within the art of integrated circuit manufacture. For example, Chi, in U.S. Pat. 5,173,437 discloses a MOSFET, portions of which are formed simultaneously with a double layer polysilicon capacitor within an integrated circuit. In addition, Natsume, in U.S. Pat. 5,356,826 discloses a MOSFET, portions of which are formed simultaneously with a double layer polysilicon capacitor and a polysilicon resistor within an integrated circuit.
Desirable in the art are adjunct methods and structures which supplement Lightly Doped Drain (LDD) ion implant structures in controlling the Hot Carrier Effect (HCE) in advanced MOSFETs. Particularly desirable are adjunct methods and structures which assist in controlling the Hot Carrier Effect (HCE) within advanced MOSFETs while simultaneously facilitating formation of other integrated circuit devices, such as double layer polysilicon capacitors and polysilicon resistors, within the integrated circuit within which is formed the MOSFET having enhanced Hot Carrier Effect (HCE) immunity.